Tessent Streaming Scan Network: A practical DFT approach for hierarchical and flat designs
Modern integrated circuit designs present huge challenges in their size, complexity and limited access, making them difficult to test using traditional scan access methods.
Traditional compression methods are dependent on limited top-level resources, forcing a compromise between pattern count and test time while maintaining test coverage targets. Designs with complex power domain strategy may require some design partitions to remain inactive while adjacent partitions are active, forcing the DFT to find cumbersome paths to route around those powered-down domains.
This webinar is for anyone inserting DFT on a design, regardless of running flat ATPG or scan pattern retargeting for a hierarchical design. It will cover advantages of using Tessent Streaming Scan Network (SSN), a packetized scan delivery mechanism that efficiently delivers scan patterns for heterogenous and identical cores independent of top-level I/O resources.
Who would benefit most from watching the Tessent Streaming Scan Network: A practical DFT approach for hierarchical and flat designs webinar:
- DFT Design Engineers/Managers
- IC Design Engineers/Managers
- Production Operations Teams
- Automotive IC Design Engineers/Managers
What can you learn from this webinar:
- How to manage modern challenges with Integrated Circuits and DFT
- New access mechanism for scan content delivery
- Improve productivity by reducing DFT planning effort and implementation time
- How SSN enables plug-and-play DFT architecture
- How to enable DFT solutions using SSN for designs running flat ATPG or scan pattern retargeting in hierarchical designs
- Reduce test power and simplify silicon bring-up
Meet the speaker
Christian Dodd
Senior DFT Architect
Christian Dodd is a Senior DFT Architect with Tessent supporting customers and helping them adopt and implement state-of-the-art DFT technologies and methodologies. A Design-For-Test (DFT) enthusiast, Christian has over 30 years of experience in the Semiconductor industry working with the likes of Motorola, Cadence, Atmel, Wolfson Microelectronics, Cirrus Logic, Graphcore and Siemens. He is responsible for managing DFT teams and as an individual technical contributor implementing DFT for a wide and varied range of market segments including HPC, AI, Complex SoC, Automotive and Mixed Signal. Additional experience gained in complementary areas including P&R, Product & Test Engineering, Quality & Reliability and Failure Analysis and Analogue Test.