Siemens is developing technologies to help companies build and deliver more sophisticated AI products.
Moore’s Law is being rejuvenated by AI/ML after capacity fears slowed it down. Later this year, estimates put AI/ML design capacity between 5 billion and 10 billion gates — huge capacity for a single design. Designs will go back to what Moore’s Law is supposed to do. AI/ML is imposing tremendous capacity needs on the market, and these designs also present a challenge to the chip verification market. While the processor may be a relatively simple design, the AI/ML space needs to deploy many of them and scale quickly. Another consideration is software that must be verified along with hardware.
Developers of complex IC Designs and the systems they support face new levels of familiar challenges: How to get the product to market as quickly and efficiently as possible, with the required level of quality? The best way to harness systemic complexity of large AI designs and turn it into a competitive advantage is to embrace technological solutions that provide system level visibility throughout the design and deployment of the device.
Leveraging machine-learning algorithms to improve IC design tools so that they can deliver better results for customers faster.
As we all know, ML is useless without data. The more data that’s produced, the more ML can be called in to sort and develop something meaningful from that data. What’s lucky for us is that EDA tools themselves produce an enormous amount of data. Process manufacturing generates a large amount of data, and users can produce their own proprietary data and requirements (for training). So, theoretically there isn’t a shortage of data. In fact, when leveraging ML for EDA, the question becomes: What data sets can be leveraged effectively for what tool functions?
We have technologies that have AI/ML enhancements, and most of these are in the realm of design and functional verification, library characterization simulation, design for test, embedded analytics and physical design, verification and manufacturing.
What will you learn
Who should attend
Senior Application Engineering Manager - SVSD, India
Pradeep Salla heads the Verification team at Siemens EDA, part of Siemens DISW. He is responsible for driving and supporting the Verification technology and develop markets for Siemens EDA. Prior to Siemens EDA, he has worked in various organizations such as Renesas Electronics, Nokia & MindTree and has a total experience of about 18 years in Functional Verification. Pradeep serves on various industry forums like International VLSID Conference, IESA Vision Summit, DAC and currently is the General Chair of DVCon India. He received his Master’s in Electrical Engineering from North Carolina State University and B.E from Bangalore University. His areas of expertise include architecting reusable testbenches at IP, Subsystem and SoC level, Power Aware verification, Design for Software Debug among others.