SW-enabled validation: Ensuring correct SoC and system operation with real workloads

Webinar Overview

There’s nothing worse than thinking you’re close to the finish line of validating your Soc design, and you find the embedded SW isn’t working properly on the RTL. After doing all of that work you have to re-trace your steps to detect just what went wrong and locate exactly where the issue is. Is it in hardware or software? Or both?

This webinar explains how adding a SW-enabled validation environment to an existing hardware verification environment yields many benefits. A SW-enabled validation solution including, Veloce HYCON, Veloce Codelink and Veloce Vprobe provides the functionality needed without requiring changes to the software or hardware design. These multi-faceted tools support multi-core, multi-CPU environments and offer the ability to single step forward and backward, as well visibility up and down the call stack. This allows teams to see what the software and hardware are each doing at the precise time when a bug is encountered.

Attend this webinar to learn how the Veloce Platform and tools for SW-enabled validation can link your hardware verification environment to the SW executing on the CPU.

What you will learn

• How to achieve 100% visibility into HW/SW interactions for debug, analysis, and co-validation
• The advantages of early software bring-up, architecture exploration, and power/performance profiling with realistic workloads
• The ways that end-to-end software-enabled validation improves product quality

Who should attend

• Software validation
• SoC verification and validation
• System design and validation