There’s nothing worse than thinking you’re close to the finish line of validating your Soc design, and you find the embedded SW isn’t working properly on the RTL. After doing all of that work you have to re-trace your steps to detect just what went wrong and locate exactly where the issue is. Is it in hardware or software? Or both?
This webinar explains how adding a SW-enabled validation environment to an existing hardware verification environment yields many benefits. A SW-enabled validation solution including, Veloce HYCON, Veloce Codelink and Veloce Vprobe provides the functionality needed without requiring changes to the software or hardware design. These multi-faceted tools support multi-core, multi-CPU environments and offer the ability to single step forward and backward, as well visibility up and down the call stack. This allows teams to see what the software and hardware are each doing at the precise time when a bug is encountered.
Attend this webinar to learn how the Veloce Platform and tools for SW-enabled validation can link your hardware verification environment to the SW executing on the CPU.
Product Manager, Scalable Verification Solutions Division
Andy Meier is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr. Product Marketing Manager at Siemens EDA, Product Marketing Manager at Mentor Graphics, Solution Product Manager at Hitachi Data Systems, Director of Application Engineering at Carbon Design Systems, Senior Verification Engineer at SiCortex. He holds a Bachelor of Science degree in Engineering and Computer Engineering from Worcester Polytechnic Institute in Worcester, Mass.