Standardization of chiplet models

With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions.

This is driving an emerging trend to disaggregate what typically would be implemented as a single homogeneous, system-on-silicon (SOC) ASIC device into discrete, unpackaged ASIC devices, otherwise known as chiplets.

As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the industry to standardize on a set of interface protocols that offer plug-and-play compatibility between different suppliers' chiplets, creating a true open ecosystem and supply chain.

Integrating these multi-vendor chiplets into a heterogeneous package assembly will also require chiplet vendors to provide their customers with a standardized set of design model deliverables that will ensure operability in the end users EDA tool design workflows.

This video provides an overview and update on the Open Compute Platforms Chiplet Design eXchange (CDX) project.

• Chiplet Integration workflow
• Chiplet Design Exchange (CDX)
• Chiplet models and design kit
• CDXML/JEP30 and adoption by EDA industry
• Chiplet workflow development in CDX