Stackup Design for Signal Integrity Simulation

We all want simulators that can model detailed electromagnetic behavior and produce highly accurate results, but what happens if you build something different than what you simulated? While no one does that deliberately, the fact is – it happens all the time because the details of the materials and processes used to build the board aren’t accurately represented in the simulation model. As speeds go faster and margins get smaller, the small details of board fabrication – like plating layer thickness and conductivity, or metal roughness on core vs. prepreg layers – can significantly impact design performance. In order to ensure simulation results are accurate, it has become critical to model and analyze a board as it will be manufactured – instead of using traditional methods.

This webinar will introduce Z-planner, an advanced tool for the design and analysis of PCB stackups, traces, and via designs. We’ll show you how to evaluate PCB tradeoffs and create a detailed board model that ensures that the detailed design simulations you perform reflect the behavior of the board as it will actually be built instead of reflecting the behavior of a board as you wish it could be built.

What you will learn:

• How PCB manufacturing impacts signal integrity
• How to take an existing simulation stackup and make it "real", ensuring it can be manufactured
• How to work with multiple PCB fabricators and compare alternative stackups
• How to ensure your PCB stackup is real, before  you start running extensive design solutions

Who should attend:

• SI & PI specialists looking to make their simulations more accurate
• Hardware system designers looking to accelerate their design's transition into manufacturing
• New Product Introduction (NPI) engineers working with PCB fabricators
• Hardware design managers looking to improve the interface between design & manufacturing