on-demand webinar

Space Codesign High-Level Synthesis for Hardware/Software Architectural Exploration of an Inferencing Algorithm

Complete Seminar Recording, Slides, and Q&A

Estimated Watching Time: 200 minutes


Seminar with Space Codesign: presents a design flow including HW/SW co-design and HLS that allows developers to migrate compute intensive functions from software running on an embedded processor to a hardware based accelerator.

Edge devices of all types are getting smarter, with the ability to listen to us, understand our gestures, and even recognize us. This intelligence comes from the inferencing capabilities of deep neural networks. Inferencing is compute intensive and can easily overwhelm embedded processors or the limited power budgets of some edge systems. One way to address this is to move the computationally complex parts of the inferencing algorithm into hardware, where it can be performed faster and more efficiently.

A practical way to approach this is to use a virtual platform which is a software representation of the hardware platform (System-On-Chip or board), modeled at a high enough level of abstraction where software execution may be simulated without the complexities of low-level hardware. The platform can execute the entire software stack, including the OS and the hypervisor, on an Instruction Set Simulation (ISS) model of the processor, which in turn is simulated on a host computer.

This seminar will present a design flow including HW/SW co-design and High-Level Synthesis (HLS) that allows developers to migrate compute intensive functions from software running on an embedded processor to a hardware based accelerator as a loosely coupled bus-based peripheral. Relocating a function from software to hardware improves performance and efficiency of the design.

The example design used in this seminar will implement a wake word algorithm. Wake word algorithms need to continuously monitor an audio input stream for one or more keywords, and wake the system if the word is found. It requires significant audio pre-processing, as well as an inference for a deep neural network. These calculations are performed multiple times per second. Migrating functions to hardware will dramatically improve battery life in this application.

You will see how SpaceStudio, from Space Codesign, covers the algorithm creation/capture phase and algorithm validation on a virtual platform. Architecture optimization such as exploration to partition the algorithm between multicore CPU and FPGA can be performed with full system compilation for execution on a physical board.


  • Intro and Overview of High-Level Synthesis 
  • Algorithm Description 
  • Introduction to SpaceStudio 
  • HW/SW Partitioning with SpaceStudio: A Practical Case Study - Part 1 
  • Designing with HLS 
  • Architecture refinement at the C++ level 
  • HW/SW Partitioning with SpaceStudio: A Practical Case Study - Part 2 
  • Results and conclusion  
  • Wrap-up and Q&A

Who Should Attend:

  • RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
  • Architects or hardware/software-aware algorithm developers in the field of, voice recognition, machine and deep learning that are interested in rapid and accurate exploration of power/performance metrics.
  • New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for deep learning markets.

What you will learn:

  • How SpaceStudio coupled with Catapult is used to implement a voice recognition algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
  • How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such.
  • How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
  • How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
  • Customer's experience using HLS for Wake Word and AI
  • How HLS can help get from algorithm to critical FPGA demonstrators faster than with traditional RTL flow
  • How Catapult HLS development methodology has enabled IP block development

Meet the speakers

Space Codesign Systems

Hubert Guérard


Hubert Guérard is the CEO at Space Codesign Systems whose flagship product, SpaceStudio, eases the design flow of application into hardware centric implementation. He graduated from Polytechnique Montréal where the technology was born. Over the years, he held several positions from engineer to director of engineering. He currently oversees the development of SpaceStudio and is expanding the solution to new market.

Space Codesign Systems

Anthony Dentinger

System Designer

Anthony is a technical lead of SpaceStudio, the flagship product of Space Codesign Systems. His knowledge of both enterprise and research environments, his expertise in the C++ and high-level synthesis ecosystems, as well as of embedded systems development, have proven invaluable in the design and coordination of some of the major undertakings of the company. Anthony holds a Bachelor of Engineering in Computer Science from Polytechnique Montréal, where SpaceStudio was born.

Siemens EDA

Stuart Clubb

Technical Product Management Director

Siemens EDA

Sadhvi Praveen

HLS Technologist

Sadhvi Praveen is a Product Engineer in the Catapult team, focusing on High-Level Synthesis for FPGA/ASIC. She has been with Siemens EDA for over 4 years, holding a variety of roles in pre-sales and technical marketing teams. She holds a Master's degree in Computer Engineering from Rochester Institute of Technology.

Siemens EDA

Russell Klein

HLS Program Director

Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor.

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