If you are designing using FinFET technologies and creating products that compete on low-power, you know leakage will be reduced compared to planar technologies -- but you now need to consider every opportunity to save dynamic power. This means it is now necessary to create power-efficient RTL.
In this webinar, we will describe how PowerPro's platform supports multiple use case scenarios for the creation of low-power RTL, including early exploration for low-power with RTL in development, guided and automated optimization with formal equivalency proofs for IP power optimization, and fast and accurate RTL power analysis for block and chip level.