If you are designing using FinFET technologies and creating products that compete on low-power, you know leakage will be reduced compared to planar technologies -- but you now need to consider every opportunity to save dynamic power. This means it is now necessary to create power-efficient RTL.
In this web seminar, we will describe how PowerPro's platform supports multiple use case scenarios for the creation of low-power RTL, including early exploration for low-power with RTL in development, guided and automated optimization with formal equivalency proofs for IP power optimization, and fast and accurate RTL power analysis for block and chip level.
What you will learn:
Early exploration for low-power with RTL in development
Guided and automated optimization with formal equivalency proofs for IP power optimization
Fast and accurate RTL power analysis for block and chip-level
How to create power-efficient RTL
Who should attend:
RTL designers interested in maximum reduction of switching/dynamic power in their blocks/designs especially those targeting FinFet technologies
Methodology engineers who are focusing on low-power design flows
RTL project managers interested in overall power reductions in their designs beyond the typical clock and memory gating