on-demand webinar

Smarter DFT architecture for advanced SoCs



The basic issue with DFT for advanced SoCs is the size of problem and the need to have a plan to manage DFT functions at the SoC level. We will show how a smart hierarchical DFT methodology dramatically simplifies the problem. Core level DFT insertion and pattern generation can be complete at the core level plugged into the SoC later. Knowledge of the core details and setup is automated with a plug-and-play infrastructure.

The next evolution of SoC level DFT is packetized data delivery. Advantages of this technology is optimization and balancing of data to cores independent of the optimized core compression and any size chip level bus down to one bit. In addition, there are significant advantages of simplified DFT timing closure and support for any number of duplicate cores. Attendees will learn how to use smart solutions to simplify the DFT methodology and improve results and time-to-market.

Meet the speakers

Siemens EDA - Tessent

Ron Press

Director of Technology Enablement

As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference(ITC)Steering Committee, and a Golden Core member of the IEEEComputer Society, and a Senior Member of IEEE. Ron haspatents on reduced-pin-count testing, glitch-free clock switching, and on 3D DFT. Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a system built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. He joined the Mentor DFT organization in 1997.

Siemens EDA

Joe Reynick

Product Engineering Manager - Tessent

Joe Reynick is a Product Engineering Manager for the Tessent product family at Siemens Digital Industries Software, where his responsibilities include packetized scan and Tessent Multi-die support. Joe has more than 38 years of industrial experience in ASIC Design, DFT, IP, Test and EDA technologies.

Joe served as Director of DFT Solutions at eSilicon, a pioneer of the fabless ASIC and COT models, from 2001 to 2020. His role included building and managing the worldwide DFT team, as well as the silicon bring-up/IP verification labs. His responsibilities included several 2.5D/5.5D projects.

Joe developed his passion for DFT as a member of the technical staff at AT&T/Lucent Bell Laboratories with a focus in the areas of DFT, ASIC Design, Optoelectronics, Test and EDA from 1984 to 2001.

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