On-Demand Webinar

Smarter DFT architecture for advanced SoCs

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Tessent

The basic issue with DFT for advanced SoCs is the size of problem and the need to have a plan to manage DFT functions at the SoC level. We will show how a smart hierarchical DFT methodology dramatically simplifies the problem. Core level DFT insertion and pattern generation can be complete at the core level plugged into the SoC later. Knowledge of the core details and setup is automated with a plug-and-play infrastructure.

The next evolution of SoC level DFT is packetized data delivery. Advantages of this technology is optimization and balancing of data to cores independent of the optimized core compression and any size chip level bus down to one bit. In addition, there are significant advantages of simplified DFT timing closure and support for any number of duplicate cores. Attendees will learn how to use smart solutions to simplify the DFT methodology and improve results and time-to-market.

Meet the speakers

Siemens EDA - Tessent

Ron Press

Director of Technology Enablement

As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference(ITC)Steering Committee, and a Golden Core member of the IEEEComputer Society, and a Senior Member of IEEE. Ron haspatents on reduced-pin-count testing, glitch-free clock switching, and on 3D DFT. Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test. He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a system built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. He joined the Mentor DFT organization in 1997.

Siemens EDA - Tessent

Joe Reynick

Technology Enablement Engineer

Joe has over 37 years of industrial experience in the ASIC Design, DFT, Test, and EDA arenas, including more than 300 career tapeouts. From 2020 to present: Technology Enablement Engineer (TEE) at Mentor and Siemens DISW with a focus on Streaming Scan Network (SSN) & overall DFT Architecture as well as a 2.5D/3D DFT and IP test advisory role. From 2001-2020 Joe was “Director of DFT Solutions” at eSilicon Corporation, which kickstarted the fabless ASIC market. Joe’s overall responsibility for all DFT projects included ASICs, COT and IP core development and developed and managed a world-class DFT and IP test teams in the USA, Asia, and EU. He also built and managed worldwide silicon bring-up and verification labs with Advantest ATE as well as DFT architecture for all ASIC and COT projects. From 1984-2001, Joe developed his passion for DFT as a Member of Technical Staff at AT&T/Lucent Bell Laboratories and was instrumental in DFT, ASIC Design, Optoelectronics, Test, and DFT tool development/applications. Joe has a patent on voltage stress with delta-Iddq for reliability testing.

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