Shared Bus interface insights

Tessent Shared Bus Access

A Shared Bus interface provides a common access port to several memories. This architecture enables scalability when adding memories inside a module and at the same time preserves a fixed footprint at the module boundary for memory BIST access. A typical application for Shared Bus interfaces would be testing memories that are inside processor core modules. This ensures optimal testing of memories with minimal impact on functional timing and performance.

The terms Shared Bus memory cluster or Shared Bus cluster refer to a module that provides access to multiple memories using a common Shared Bus interface. A logical memory is an address space that is composed of one or more physical memories. Library files provide descriptions of the Shared Bus memory cluster module, shared interface ports, and information about the logical and physical memories.

Who should attend:

All DFX, DFT, test, and management who are interested in creating and
utilizing a reliable repair infrastructure memory and functional
purposes.

This webinar:

• attempts to walk through the steps required to create
  these library files and explains the tool flow that performs the
  generation, insertion, and verification of embedded test hardware.
• explains the fundamental concepts and advantages of
  enabling a Shared Bus architecture for Memories within design cores.
  With new requirements in Automotive, AI, and processor applications;
  the need to utilize functional access to memories & testing them is
  gaining prominence and is of paramount interest to reduce performance
  degradation.

What you will learn:

• Understand the Shared Bus methodology
• Learn about Cluster, Logical and Physical views
• MemoryBIST implementation and pattern generation examples.
• Discuss MemoryBIST flow variations and handling
• Understanding repair implementation in a Shared Bus environment