Power Leaks in Your RTL? - Fix Them with PowerPro
Power consumption problems are now the #2 driver of respins! The greatest impact on power is at RTL and above, but RTL teams often don’t have the detailed expertise, tools, or time left in their project schedules to focus on power. The PowerPro platform is the proven leader in RTL power optimization, and in this webinar, we look at how the new PowerPro visualization and debug capabilities take its leading optimization technology further to help designers understand precisely where their RTL is “leaking power,” and what actions they can take to improve the design and confirm if they have accurately fixed the problem.
What You Will Learn
- Understand precisely where your RTL is “leaking power”
- Actions that can improve the design
- RTL power optimization
- New PowerPro visualization and debug capabilities
Who Should View
- RTL Designers/Project leads
- Low-Power Methodology specialists
- RTL designers
- Power architects
- Project managers
Meet the speaker
John Reed
Senior Application Engineer
John E. Reed has 20 years of experience in the ASIC and EDA industries. He spent the first 10 years as a Design Engineer at IBM and then worked as a Verification Engineer at Intel and Sigmatel. He has now been in the EDA industry for 10 years, first transitioning to Novas as an Application Engineer. Now he is a Senior Application Engineer at Siemens EDA.