Power is EVERYWHERE. In multiple power-critical markets, a methodology for early, continuous, and accurate power metrics throughout the RTL development cycle is required. In this webinar, we show how PowerPro®’s unique combination of “physically aware” synthesis and deep-sequential analysis can be used to achieve power estimations on RTL that are within ±15% accuracy to post-place and route, but in a fraction of the time. Combining this with the ability to also deliver near-sign-off gate-level average and peak power, enables design teams to have a complete power regression methodology from block to SoC.
What will you learn:
How to achieve power estimations on RTL that are within ±15% accuracy to post-place and route, but in a fraction of the time
Near-sign-off gate-level average and peak power
Power regression methodology from block to SoC
Who should attend:
RTL Designers/Project leads
Low-Power Methodology specialists