On-Demand Webinar

Part 1: Why Are High-Performance Low-Energy Applications Moving from GPUs and DSPs to FPGAs and ASICs?

Estimated Watching Time: 55 minutes


Transistor counts and performance of integrated circuits are reaching their peak. Artificial intelligence is emerging as the next "big thing" in areas such as automated driving, security, language recognition and translation. Most of its algorithms are embarrassingly parallel, thus easing the creation of new services and the growth of existing ones, without requiring faster clock speeds.

Memory access bandwidth and energy-per-computation become the new performance indices. GPUs (e.g. Nvidia Drive PX-2) and DSPs (e.g. Mobileye Vision Computing Engines and Vector Microcode Processors) offer very high-parallelism within the scope of a fully programmable platform. However, they need to fetch and decode every instruction, and must have a relatively fixed architecture, which leads to wasted energy.

FPGAs, on the other hand, also exploit the latest technology generations, but provide a fully customizable architecture, in particular with respect to the memory hierarchy. However, they are still fully programmable, and can thus be quickly customized to new algorithms and emerging applications.

This webinar will cover high-parallelism applications from the domains listed above, and will discuss why the quest for lowest energy consumption, in order to reduce packaging and operational costs, is driving implementation platforms to include FPGAs for tasks that were traditionally the domain of GPUs and DSPs. This webinar is the first in a two part webinar series. The second webinar in this series is Part 2: Adapting Software Algorithms to Hardware Architectures for High Performance and Low-Power.

Who should attend:

Programmers and managers interested in learning the trade-offs between CPU/GPU/DSP based platforms and those including CPUs and FPGAs

What you will learn:

  • Key architectural characteristics and differences between GPUs and FPGAs

  • Memory architectures and access mechanisms on GPUs and FPGAs

  • Programming models based on high-level languages like OpenCl

Meet the speaker

Politecnico di Torino

Luciano Lavagno


Luciano Lavagno received his Ph.D. in EECS from U.C.Berkeley in 1992. Luciano co-authored four books and over 200 scientific papers. He was the architect of the POLIS HW/SW co-design tool and one of the architects of the Cadence CtoSilicon High-Level Synthesis tool. He is a professor with Politecnico di Torino, Italy and, also, a consultant for the Catapult High-Level Synthesis group of Siemens EDA. His research interests include High-Level Synthesis, HW/SW co-design, and design tools for wireless sensor networks.