To meet high-performance computing (HPC) targets, specific challenges must be considered. Because the margins for achieving design closure on HPC designs at signoff are very small, every step of the physical implementation flow needs to address PPA metrics and avoid pessimism. HPC designs also need effective datapath skewing, from place optimization all the way through route optimization, to meet their challenging frequency targets.
In this webinar you will learn:
- How the detail-route–centric architecture of the Siemens Aprisa digital implementation design solution makes it possible to derive the push-and-pull offsets during place optimization and effectively realize them during route optimization
- How Aprisa correlates extremely well with the STA and DRC Signoff tools, allowing designers to adopt the flow very quickly for their advanced node designs
- About an HPC at an advanced process node implemented in Aprisa using its out-of-the-box flow, and how the above technologies helped achieve the desired frequency target.