Hardware architecture has a huge impact on RTL "quality of results" when deploying High-Level Synthesis (HLS). In this on-demand seminar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in the output RTL.
What you will learn:
Fundamental filter architectures and HLS coding style
Windowing for efficient image processing
Delay line implementation with a single-port RAM
Who should attend:
RTL designers and managers interested in moving up to HLS
Existing HLS users
Designers and managers involved in algorithm to RTL translation
Meet the speaker
Technical Product Management Director
Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.