On-Demand Webinar

Optimizing complex AI and ML SoC designs: the role of system-level data


Find out how companies developing complex AI / ML SoCs can deploy functional data and analytics to meet demanding chip performance targets and validation schedules.

Hosted by Siemens Fellow Gajinder Panesar and Tessent Embedded Analytics Product Manager Richard Oxland, this new webinar will discuss the challenges of creating highly complex manycore AI / ML implementations, and show how system-level visibility of SoC functionality helps turn complexity into a competitive advantage - in development, validation, and throughout the deployed lifetime of the device.

What you will learn:

This webinar highlights the benefits of system-level visibility into the operation of complex, manycore chips for AI and ML computation tasks; and the value delivered by those functional insights, from chip validation through to deployment in the end application.

Who should attend:

  • System-on-chip architects

  • Verification engineers

  • Validation engineers

  • Embedded software architects and developers


The move to AI and ML-type workloads has created an explosion in SoC complexity, as developers try to find a balance between speed, cost, and application flexibility. A common theme lies in the adoption of manycore architectures designed specifically to deal with such workloads – in the cloud, in HPC-type environments and at the edge. The extensive use of parallelism provides an effective response to issues such as the power wall – which makes further frequency scaling near impossible – and the need to operate on large, often sparse, data structures.

Though these parallel arrays can in principle deliver high compute performance, they entail growing complexity in terms of system validation and system software development. The need for flexibility to deal with a range of applications translates into an embedded system that is increasingly difficult to validate, optimize and deploy effectively.

The challenge goes well beyond the problem of debugging the compute cores, dimensioning interconnects and assessing the performance of memory controllers. Today’s AI and ML chip development teams need to put in place data gathering and analytics infrastructures that give both fine-grained information where it is needed, and system-level visibility of the functional operation of the entire device. Tessent Embedded Analytics from Siemens is a suite of silicon IP, software tools and libraries that provide a platform for system-level visibility and functional analytics, together with best-in-class expertise in designing the right solution for the most complex chip architectures. Our customers benefit from our experience and expertise in architecting solutions to harness SoC complexity through the whole lifecycle.