on-demand webinar

Oak Ridge National Lab (ORNL): A Spiking Neural Network Architecture for Ultra-low Power and Ultra-low Latency Computing

Estimated Watching Time: 23 minutes

Share

ORNL with the help of the Siemens EDA tools, including Catapult HLS, the neuromorphic accelerator is being adapted from an FPGA prototype to a more capable and lower-power ASIC implementation.

The U.S. Department of Energy (DOE) has called on the national labs to strengthen their microelectronics capabilities. In response, Oak Ridge National Lab (ORNL) has formed an internal microelectronics initiative with a focus on AI for scientific applications and energy-efficient computing. Researchers in the Architectures and Performance Group at ORNL have developed a digital neuromorphic architecture specifically designed for scientific applications that require ultra-low latency. With the help of the Siemens EDA tools, including Catapult HLS, the neuromorphic accelerator is being adapted from an FPGA prototype to a more capable and lower-power ASIC implementation. In collaboration with the Sensors and Electronics Group, the neuromorphic processor is also being re-target towards another import DoE mission of nuclear safeguards. This effort is exercising Siemens analog and mixed-signal tooling to integrate the neuromorphic processor with the sensing elements more closely by exploring efficient analog encoding neurons and event-driven gamma-ray detection. This presentation will give a brief overview of nuclear safeguards and other scientific applications at ORNL. Then, we will present the work done so far to develop the ASIC neuromorphic processor, the progress and plans for the mixed-signal processing and sensor subsystem, and finally, the dataset and algorithmic details we are leveraging to demonstrate the project’s capabilities.

Meet the speaker

Oak Ridge National Lab (ORNL)

Brett Witherspoon

Embedded Hardware and Software Engineer

Brett Witherspoon is an Embedded Systems Hardware & Software Engineer in the Sensors and Electronics Group at ORNL. He specializes in electronics design and analog/digital signal processing for low-power embedded systems. For much of his career, he has researched practical applications of AI/ML for wireless communications and sensing. Highlights include winning the DARPA Spectrum Challenge (2013-2014) and placing fourth in the final round of the DARPA Spectrum Collaboration Challenge (2016-2019) as an R&D engineer at Tennessee Technological University and later as an independent consultant. Since joining ORNL in 2021 he has focused primarily on radiation monitoring systems and embedded neuromorphic systems.

Related resources

SLEC System Factsheet
Fact Sheet

SLEC System Factsheet

SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models

Catapult High-Level Synthesis and Verification Fact Sheet
Fact Sheet

Catapult High-Level Synthesis and Verification Fact Sheet

Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.

StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
White Paper

StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses

StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.