NXP: RTL Power Optimization - Applying Best Practices to Overcome Low-Power Design Challenges

Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality in SoCs is rapidly outpacing the power budget. Power must be considered at every stage of chip design including performance, reliability, and packaging. Waiting to address power until late in the design cycle – post-netlist or during physical implementation – can be extremely costly. The design may overrun the power budget, overheat, or have long term reliability issues that cannot be addressed at the gate level, layout or package selection. The best point in the design cycle to address power is at the beginning during the architectural and RTL stages. The earlier power analysis and optimization starts, the more likely a chip will meet its power objectives. In this presentation, you will learn the best practices for applying RTL power optimization. These practices are essential for realizing low-power, energy efficient designs, can help you meet power budgets, mitigate potential reliability issues arising out of power and discover thermal issues early to take corrective action. NXP will present their perspective on applying these techniques. You will learn how Siemens EDA’s PowerPro low-power design platform helps simplify low-power design for RTL designers and allows coarse as well as fine grain power analysis and optimization to achieve truly low-power, energy efficient designs.