on-demand webinar

Microchip: Building flexibility, agility, and automation into a complete Aprisa flow

Estimated Watching Time: 20 minutes

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Microchip’s mixed signal digital requirements demand a flexible approach beyond the standard ASIC flow. Microchip collaborated with Siemens to develop a robust, unified Place & Route flow centered on Aprisa, allowing adaptability to project specific needs (libraries, corners, metal stacks), improved time to flow maturity, and automation of common but critical tasks with a focus on ease of use and fast turnaround.

The presentation discusses the partnership and highlights the flow’s differentiating features and automation that help users reach flow stability quickly, delivering significant impact across multiple internal projects.

Meet the speakers

Microchip

Scott Krueger

Senior Manager – Design Engineering

Scott has over 25 years of Automated Place & Route experience, and nearly 15 years managing a team of APR engineers. I started at Microchip (through two acquisitions) in April of 2002, stepping into a management role shortly after Microchip acquired SMSC in 2012. I have led a team of APR engineers in the US, and now teams in Penang, Malaysia. I have experience in both block and chip level APR, with emphasis on semi-custom APR designs. I spent my formative years in Microchip supporting the Automotive Infotainment Systems Business Unit, so additional emphasis was on creating flows to meet the astringent requirements of automotive designs. Finally, I have a passion for flow automation. I have been working directly with the Aprisa tool for over two years now, and my team has been instrumental in developing an Aprisa flow that meets the needs of all the Business Units that we support.Outside of the office, I enjoy soccer, homebrewing, soccer, hiking, and soccer.

Microchip

Alejandro Hernandez

Senior Engineer I - Design

Alejandro Hernandez is a semiconductor physical design engineer and software builder specializing in advanced APR automation, EDA tooling, and workflow optimization with 5 years of experience.

With over 20+ successful digital block tapeouts, he is also in charge of Microchip’s Aprisa APR flow development.