Machine Learning: How HLS Can Be Used to Quickly Create FPGA/ASIC HW for a Neural Network Inference Solution

HLS (High-Level Synthesis) has the unique ability to go from complex algorithms written in C to RTL enabling accurate profiles for power and performance for an algorithm's implementation without having to write it by hand. Neural Networks are typically developed and trained in a high-performance compute environment but in many cases, the inference solution can be reduced and then HW accelerators are the only solution to meet power and real-time requirements. This session reviews the consideration around fast HW prototyping for validating acceleration in Neural Networks for Inferencing vs highest performance implementation and the tradeoffs.

This webinar is part 4 of the seminar Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning.

What you will learn:

• How HLS can be used to implement an example Computer Vision
  Algorithm in either an FPGA or ASIC technology and the trade-offs for
  power and performance. You will walk away with examples, building
  blocks, etc that are completed and can be referenced.
• How to achieve faster but complete verification signoff in an HLS
  flow measuring quality, coverage; saving days and weeks in
  verification costs
• How HLS can be applied in multiple ways to implement acceleration
  for Deep Learning and in particular Convolutional Neural Networks. You
  will walk away with examples, building blocks, etc that are completed
  and can be referenced.

Who should view:

• RTL Designers or Project Managers interested in moving up to HLS
• Architects or Algorithm developers in the field of image processing,
  computer vision, machine and deep learning interested in rapid and
  accurate exploration of power/performance metrics
• New Project teams with only a few designers and multiple SW experts
  wanting to rapidly create high-performance FPGA or ASIC IP for
  Computer Vision or Deep Learning markets