on-demand webinar

Leveraging RTL Power Exploration to Achieve the Lowest Power Implementations

Estimated Watching Time: 18 minutes


Leveraging RTL Power Exploration to Achieve the Lowest Power Implementations

Power consumption impacts multiple applications and markets such as handheld, workstations, and servers to name a few. Because the greatest opportunities for optimizing power are at the micro-architecture and RTL design stages, the PowerPro Platform provides an interactive approach to power exploration and power reduction at RTL. This platform uses a unique architecture that eliminates iterations through simulation and synthesis, giving immediate power feedback. This web seminar will show how PowerPro easily identifies where power is wasted; from the micro-architectural level to memory, register, and combinational elements. The platform provides “what-if” analysis, interactively assessing the impact on power due to potential design transformations.

What you will learn:

  • Survey results: Power reduction- who is doing it and when
  • Overview of the PowerPro platform
  • Interactive RTL analysis and exploration environment
  • 3 detailed examples of RTL power reduction guidance
  • Optimizing further with design exploration
  • Examples and customer results

Who should attend:

  • RTL designers
  • Power architects
  • Project managers

Meet the speaker

Siemens EDA

Stuart Clubb

Technical Product Management Director

Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.

Related resources