Keynote: Computer Vision, Machine Learning and HLS – Some History, Trends and Highlights

Image processing for computers has been around for a long time, as has AI (Artificial Intelligence) and learning machines and High-Level Synthesis (HLS); actually decades. So, why now for all of the buzz? Why is it so more applicable now? This keynote presents many of the market trends, future growth areas around computer vision and machine learning along the current capabilities of HLS that are naturally bringing these technologies together to rapidly accelerate the delivery of high-performance, low-power systems from rapidly changing algorithms.

This webinar is part 1 of the seminar Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning.

What you will learn:

• How HLS can be used to implement an example Computer Vision
  Algorithm in either an FPGA or ASIC technology and the trade-offs for
  power and performance. You will walk away with examples, building
  blocks, etc that are completed and can be referenced.
• How to achieve faster but complete verification signoff in an HLS
  flow measuring quality, coverage; saving days and weeks in
  verification costs
• How HLS can be applied in multiple ways to implement acceleration
  for Deep Learning and in particular Convolutional Neural Networks. You
  will walk away with examples, building blocks, etc that are completed
  and can be referenced.

Who should attend:

• RTL Designers or Project Managers interested in moving up to HLS
• Architects or Algorithm developers in the field of image processing,
  computer vision, machine and deep learning interested in rapid and
  accurate exploration of power/performance metrics
• New Project teams with only a few designers and multiple SW experts
  wanting to rapidly create high-performance FPGA or ASIC IP for
  Computer Vision or Deep Learning markets