Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model. Discussing the use-case of using HLS for fast prototyping of a purely hardware signal path model, with focus on the required adaptations since the model was initially developed without having HLS in mind. Furthermore the audience will understand the required refinement steps (e.g. quantization, handshake between modules, applying required constraints) needed to synthesize the optimized RTL. In conclusion they will present the ease of use and the value of the HLS methodology in an industrial project.
Firmware Staff Engineer
Ana Plaiseanu is a Firmware Engineer at Infineon Technologies Romania - Sense & Control Division, working mainly on firmware development and testing for Automotive ASIC products but with an interest also in behavioral modeling and testing for automotive sensors. Ana received her bachelor degree from Polyethnic University of Bucharest, specializing in microelectronics and has a 9 year experience as Software & Firmware Engineer in automotive product lines for pressure and magnetics sensors.
Application Engineering Manager
Thomas Arndt is an Application Manager at COSEDA Technologies, focusing on system level design and simulation solutions. He has over 20 years of experience in the chip design and the EDA industry. His particular areas of expertise are in the field of digital as well as analog system design, simulation and High-Level Synthesis. Prior to joining COSEDA, he was working at the Fraunhofer Institute for Integrated Circuits, one of the largest research institutions in the field of design automation in Europe. He received his diploma in electrical engineering from the Technical University of Dresden.