Implementing design for test (DFT) in 2.5/3D designs using Tessent multi-die software
Leveraging Tessent multi-die software for comprehensive automation of highly complex DFT tasks associated with 2.5 and 3D IC designs
Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so they behave as a single device. The new Tessent Multi-die software delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.
Tessent Multi-die software automates the generation and insertion of IEEE 1838 compliant hardware, defining the IEEE test access architecture for three-dimensionally stacked or 2.5D side-by-side integrated circuits. This solution helps customers dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation ICs based on these architectures.
What will attendees of the implementing DFT in 2.5D and 3D designs webinar learn?
Join us for this webinar to learn how:
- Tessent Multi-die supports the IEEE 1838 standard, including how Tessent Streaming Scan Network (SSN) can be used as the Flexible Parallel Port (FPP) for the standard
- Tessent tools can help with DFT implementation for 2.5D/3D ICs
- Interconnect boundary scan-based patterns between the dies can be extracted using Boundary Scan Description Language (BSDL) from individual dies for 2.5D designs. Plus, unified package level BSDL creation in both 2.5D/3D devices
- IJTAG complements both 2.5D and 3D test
Who should learn about implementing DFT in 2.5D/3D designs?
Anyone who needs to investigate DFT in 2.5D/3D IC design should learn more about implementation. People in the following roles should attend this webinar:
- DFT engineers
- Test engineers
- Senior DFT managers
- CAD directors
Meet the speakers
Vidya Neerkundar
Product Manager - Tessent
Vidya Neerkundar is a Product Manager for the Tessent product family at Siemens Digital Industries Software. She has over 20 years of experience in various DFT aspects with respect to hierarchical flows and architectures including Scan, Test points, boundary scan. Vidya has worked as ASIC design engineer for Conexant prior to joining Siemens EDA. Vidya holds a Master of Science degree in Electrical Engineering.
Joe Reynick
Technology Enablement Engineer
Joe has over 37 years of industrial experience in the ASIC Design, DFT, Test, and EDA arenas, including more than 300 career tapeouts. From 2020 to present: Technology Enablement Engineer (TEE) at Mentor and Siemens DISW with a focus on Streaming Scan Network (SSN) & overall DFT Architecture as well as a 2.5D/3D DFT and IP test advisory role. From 2001-2020 Joe was “Director of DFT Solutions” at eSilicon Corporation, which kickstarted the fabless ASIC market. Joe’s overall responsibility for all DFT projects included ASICs, COT and IP core development and developed and managed a world-class DFT and IP test teams in the USA, Asia, and EU. He also built and managed worldwide silicon bring-up and verification labs with Advantest ATE as well as DFT architecture for all ASIC and COT projects. From 1984-2001, Joe developed his passion for DFT as a Member of Technical Staff at AT&T/Lucent Bell Laboratories and was instrumental in DFT, ASIC Design, Optoelectronics, Test, and DFT tool development/applications. Joe has a patent on voltage stress with delta-Iddq for reliability testing.