Learn about Aprisa digital IC implementation from real users.
Siemens’ digital implementation track at the 2023 User2User symposium featured customers sharing their experience with Aprisa in front of an IC designer audience.
In this presentation, Timothée Kocev, Place and Route Engineer at Dolphin Design, presented "Timing Closure for Ultra Low Power Design” using Aprisa digital implementation.
Dolphin Design is a provider of Semiconductor IP (including IP to enable Edge AI applications), Solutions Platforms, ASIC/SoC design and supply services.
Timothée walks us through how they used Aprisa to solve challenges they faced on their recent project. Those challenges included the need for many timing scenarios as well as floorplanning and timing closure complexity.
In this presentation, you will also learn how Aprisa’s impressive AI-driven macro placement feature can save designers weeks of manual effort, while achieving power and performance metrics, with little to no designer.
To learn more about how Aprisa’s digital implementation delivers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs visit our web page.
ASIC physical implementation engineer