on-demand webinar

Learn how Dolphin mastered timing closure in IC design with Aprisa

Estimated Watching Time: 16 minutes


Learn how Dolphin mastered timing closure in IC design with Aprisa

Learn about Aprisa digital IC implementation from real users.

Siemens’ digital implementation track at the 2023 User2User symposium featured customers sharing their experience with Aprisa in front of an IC designer audience.

In this presentation, Timothée Kocev, Place and Route Engineer at Dolphin Design, presented "Timing Closure for Ultra Low Power Design” using Aprisa digital implementation.

Ultra-low power IC design timing closure with Aprisa digital implementation tools

Dolphin Design is a provider of Semiconductor IP (including IP to enable Edge AI applications), Solutions Platforms, ASIC/SoC design and supply services.

Timothée walks us through how they used Aprisa to solve challenges they faced on their recent project. Those challenges included the need for many timing scenarios as well as floorplanning and timing closure complexity.

IC design excellence made easier


  • Aprisa was seamless to integrate and deploy into Dolphin’s existing flow.
  • Aprisa delivered design closure with an automated flow and without user intervention.
  • Aprisa achieved better leakage, better total power, and met performance targets, thus minimizing any ECOs.
  • Aprisa showcased excellent correlation with signoff tools.

In this presentation, you will also learn how Aprisa’s impressive AI-driven macro placement feature can save designers weeks of manual effort, while achieving power and performance metrics, with little to no designer.

To learn more about how Aprisa’s digital implementation delivers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs visit our web page.

Meet the speaker

Dolphin Design

Timothée Kocev

ASIC physical implementation engineer

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