HLS 101 - Fundamentals of High-Level Synthesis
High-Level Synthesis (HLS) extends the traditional design flow, providing a new and powerful approach to hardware design. It is important to understand the fundamentals of HLS and how HLS bridges the gap between the RTL designer and architect, and functional verification and RTL verification. This web seminar will provide an introduction to HLS and how an abstract, untimed algorithm representation is prepared for HLS, then transformed and optimized for power, performance and area by Catapult, resulting in high-quality RTL. Additionally, this seminar will introduce changes to the verification methodology that complement an HLS flow.
What you will learn:
- The HLS Design Flow compared to the traditional design flow
- What does the use of HLS provide?
- The fundamentals of HLS:
- Modeling for HLS
- HLS transformations / optimizations
- HLS technology mapping
- HLS scheduling
- HLS Analysis
- HLS Verification
- HLS is proven technology
Who should attend:
- RTL designers, hardware architects, and managers interested in
moving up to HLS
Related resources
SLEC System Factsheet
SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models
Catapult High-Level Synthesis and Verification Fact Sheet
Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.
StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.