High-Level Synthesis Verification Technologies and Techniques
When designing with High-Level Synthesis (HLS) many have questions regarding verification. Waiting to verify until you have post-HLS RTL is too late and too inefficient. This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
Meet the speaker
David Aerne
Verification Technologist
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.
Related resources
The benefits of being a small business with accelerated engineering
The benefits of being a small business with accelerated engineering
The Business Owner’s Brief on Accelerated Engineering and Digital Transformation
Watch this webinar to learn more about digital transformation for small and medium enterprises and the challenges they face from a survey conducted by Lifecycle Insights.
A designer’s journey from concept to manufacturing
From concept to manufacturing, learn the designer’s journey in 4 complete steps with Siemens Digital Industries Software.