on-demand webinar

High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?

Estimated Watching Time: 23 minutes

Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.

We will look at how C++ and SystemC/MatchLib High-Level Synthesis is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. For those still working in the RTL Design space, we will touch on our leading-edge technology for Power Optimization with PowerPro Designer and Optimizer. You won’t be first, but you don’t have to be last.

Meet the speaker

Siemens EDA

Richard Langridge

AE Manager

Richard Langridge works for Siemens EDA as an Application Engineering Manager. Richard has more than 30 years of experience in EDA and design, ranging from RTL Synthesis and Low-Power to High-Level Synthesis (HLS) and Formal Methods. Richard manages Low-Power engagements in a variety of Semiconductor customers.