High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?
We will look at how C++ and SystemC/MatchLib High-Level Synthesis is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. For those still working in the RTL Design space, we will touch on our leading-edge technology for Power Optimization with PowerPro Designer and Optimizer. You won’t be first, but you don’t have to be last.
Meet the speaker
Richard Langridge
AE Manager
Richard Langridge works for Siemens EDA as an Application Engineering Manager. Richard has more than 30 years of experience in EDA and design, ranging from RTL Synthesis and Low-Power to High-Level Synthesis (HLS) and Formal Methods. Richard manages Low-Power engagements in a variety of Semiconductor customers.
Related resources
Accelerate product development with simulation & testing and generative design
Learn how SMBs can accelerate product development by using simulation and testing to enhance their manufacturing process.
Simulation-driven design 101: see how using simulation early can speed up your design process
Can simulation-driven design improve your processes? Find out the advantages of simulation in design and development in this in-depth infographic.
The age of simulation-driven design is here
The age of simulation-driven design is here.