on-demand webinar

Heterogeneous Packaging Design and Verification Workflows


Image of a chip in packaging

Moore's law is difficult to maintain despite the continued reduction in semiconductor processes. With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic IC solutions.

The need for innovative packaging technologies to support system scaling demands and achieve lower system costs is driving an emerging disaggregation trend. But today's design tools and workflows don't currently support this process.

Watch this webinar to learn about the workflows required to support the design and verification of heterogeneous integration System in Package (SIP) designs.

Defining homogeneous differences from 3D IC heterogeneous SoC designs

Typical single homogeneous, System-on-Silicon (SOC) ASIC devices divide into discrete, unpackaged ASIC devices, otherwise known as chiplets. These chiplets are mounted and interconnected into a single package using high-speed/bandwidth die-to-die (D2D) interfaces that can deliver monolithic or greater functionality and performance with reduced power and cost. This multi-chiplet approach is commonly referred to as heterogenous integration (HI).

A small number of advanced users currently design these devices. The proliferation of a broader user base will require the standardization of chiplet models, D2D connectivity IP and integrated system level, ASIC and package co-design tools, flows and methodologies.

What does the heterogeneous packaging design webinar discuss?

  • Workflows required for chiplets based heterogeneous Integration
  • How STCO enables architectural exploration
  • Why Design For Test and Manufacturing Test is crucial for successful chiplets based SiP design

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