HAV U2U 2025 - NXP - NXT improves coverage and reduces time to market with a simulation acceleration methodology from Veloce CS

In this session NXP discusses how NXT accelerates simulation to reduce verification time, get higher verification coverage, and improve overall quality. Traditionally, porting simulation environments to emulation is a time-consuming effort. NXP has deployed the testbench acceleration methodology from Veloce CS. This methodology allows engineers to reuse existing verification environments as is or with minimal changes to get faster verification, allow longer workloads, achieve better coverage, and improve first silicon success.

presented by:

Ragavendar Swamisai
Director of Verification flows and Methodology
Design Enablement group, NXP