This framework is implemented using the Veloce Strato+/Veloce Strato CS and Veloce proFPGA platforms. Our Device Under Test (DUT) incorporates a wide array of interfaces, including but not limited to LPDDR5, vProbe, UART, QSPI, EEPROM, PCIe, USB, DP, RGB, and CSI. The Veloce CS platform provides all necessary Virtual Interface from VirtuaLAB/VTL and at-speed daughter boards, enabling us to expedite the verification process of our design. CIX P1, our inaugural product, has successfully met the stringent requirements for mass production. This achievement is greatly attributed to the comprehensive verification conducted on the Veloce Strato and Veloce proFPGA platforms, which ensured the robustness and reliability of our design.
presented by:
Laughing Li
Jeffery Chen
Siemens, EDA