Siemens EDA offers a silicon-proven solution for the DFT challenges of modern SoCs. This webinar describes how Tessent Streaming Scan Network (SSN) will future-proof your DFT and test implementation.
Is your traditional approach of moving scan test data from chip-level pins to core-level scan channels under pressure due to the dramatic rise in design size and design complexity? Do you follow partial or fully abutted design flows and want to decouple chip and core level DFT, and enable simultaneous testing of any number of cores with few chip-level pins? Did you know that you can change which cores you want to test on the fly in any stage of your project? Do you want to run the chip faster than what your tester supports? Are you ready to implement a technology that can optimize your test time or test data volume?
Look no further, Siemens EDA has a silicon-proven solution for all these DFT challenges! This webinar describes how Tessent Streaming Scan Network (SSN) can change the way you deliver test.
What will you learn
Who should attend