FPGA Equivalence Checking made easy

WEBINAR OVERVIEW

Even if your RTL is functionally perfect, synthesis and P&R optimizations can inadvertently slip in errors that are very hard to detect in the lab. Coincident Read Discrepancies, Incorrect Block RAM Parameter, Settings Wrong FSM, Re-Encoding, Clock gating for Low Power Issues, Undriven or Unconnected Wires, P&R Connection Issues, Incorrectly Optimized Pipelines are some of the issues found on real-world FPGA projects.

You need to enable aggressive optimizations, yet simultaneously reduce the risk of these errors appearing in the production device. In the case of the insertion of a functional trojan changes the functionality of the design similar to a bug. You need to exhaustively compare the behavior of the final netlist to the known-good RTL to prevent trojans from going undetected. Specifically, for FPGA users safely Migrating FPGA RTL to the Latest devices is a big challenge because of the device vendor has discontinued the part and absolute FPGAs have outdated safety, security, and trust features, and use too much power. Unfortunately, you can’t just cut, paste, and re-synthesize the RTL because of Original IP blocks are not available in the new FPGA libraries, Original RTL uses obsolete constructs, Impact, and mitigation of bugs in the original synthesis flow are undocumented, Netlist ECOs are not ported back to RTL, Re-synthesis may cause loss of safety compliance. As a result, an exhaustive analysis is needed to ensure the RTL functionality is preserved without error.

WHAT WILL YOU LEARN

In this session, you'll learn about formal equivalence checking approaches, including what they are, how to apply them, and the advantages of advanced formal technologies, which can be utilized by any engineer who wants exhaustive analysis to ensure the RTL functionality is preserved without error in various mentioned cases.