Fermilab: Bridging Machine Learning and Hardware Design with hls4ml and Catapult HLS
hls4ml is an open-source framework that transforms machine learning models from popular software libraries such as TensorFlow and PyTorch into hardware accelerators for FPGA and ASIC flows through High-Level Synthesis (HLS). It aims to optimize ML models for the constraints of hardware implementation while preserving accuracy. This optimization is achieved through a carefully tailored library of ML layers for HLS, a simplified set of configuration knobs, and techniques, such as quantization-aware training. The hls4ml framework facilitates a streamlined HLS design flow, allowing early estimates and accelerating the power, performance, and area optimization. Originally developed to meet the needs of particle physics experiments, hls4ml has broadened its application scope to support various scientific and industrial projects where low latency, high throughput, and energy efficiency are crucial. In this presentation, we introduce our partnership with Siemens to provide full integration with the Catapult HLS design and verification flow, describe some projects that have already benefitted from hls4ml, and outline our future directions.
Meet the speaker
Giuseppe Di Guglielmo
Senior Engineer
Giuseppe Di Guglielmo is a Senior Engineer at Fermilab specializing in system-level design and hardware acceleration for AI/ML. He currently works with scientists to develop intelligent detectors for harsh environments with ultra-low latency needs. Recent projects include designing radiation-resistant ML-enriched chips for the Large Hadron Collider and integrating ML algorithms for quantum readout and control into hardware operating at cryo temperatures. Before joining Fermilab, Giuseppe was a Research Scientist at Columbia University in New York and a postdoc at Tokyo University. He holds a Ph.D. in Computer Science and has over 10 years of experience with high-level synthesis for ASIC and FPGA design. He actively contributes to open-source communities for SoC design and AI/ML acceleration, such as ESP and hls4ml.