On-Demand Webinar

Fast RTL Verification Closure with a High-Level Synthesis Design Flow


High-Level Synthesis (HLS) has been around for many years now. Using HLS has been proven to improve design productivity and to substantially reduce verification times. As more companies move towards adopting an HLS design and verification flow, one of the most important questions engineers ask is “How do I close on coverage?”

What you will learn:

  • How to make sure C++ is clean for synthesis

  • How to close coverage on HLS-generated RTL

  • How to use Catapult Design Analyzer to find and correct coverage holes

Who should attend:

  • RTL designers

  • Hardware architects and managers interested in moving up to HLS

  • Verification engineers interested in understanding HLS-to-RTL verification flow

Meet the speaker

Siemens EDA

Michael Fingeroff

HLS Technologist

Michael Fingeroff has worked as an HLS Technologist for the Catapult High-Level Synthesis Platform at Siemens Digital Industries Software since 2002. His areas of interest include Machine Learning, DSP, and high-performance video hardware. Prior to working for Siemens Digital Industries Software, he worked as a hardware design engineer developing real-time broadband video systems. Mike Fingeroff received both his bachelor's and master's degrees in electrical engineering from Temple University in 1990 and 1995 respectively.