As semiconductor manufacturing technology continues to advance, the size and complexity of integrated-circuit designs grow exponentially. Consequently, the time-to-design-closure of an IC design project becomes not only prolonged but also uncertain. The impact is especially pressing at digital place & route stage of the design process.
In this webinar, we will give an overview of the Aprisa detail-route-centric digital implementation architecture. You will learn about Aprisa's technology for physical implementation at advanced process nodes. With this technology, timing/power/DRC and other design metrics are consistent throughout the P&R flow, which reduces iterations within the flow and helps to achieve fast time-to-design-closure for your design project.