Efficient and safe test implementation on mission critical designs

A safety critical IC is like an athlete, to run for longer duration, it must stay fit (function as designed), ensure its safety by continuously monitoring its health (monitor and report for issues), shield itself from external attack (secure from cyber-attack) and enable multiple mechanisms to safely handle failure situations. The use of effective design-for-test (DFT) technologies is imperative in smart ICs that perform self-monitoring, error detection, self-correction and address long-term reliability requirements for applications in Automotive, Medical, Datacentre, Avionics, Processors & Industrial market segments. With Siemens Tessent, customers can reduce the test cost and time to market by reducing the test data volume, do error detection, online and offline repair, reduce disruption to normal operation, and continuously monitor the device for issues while the device system is in mission operation. Siemens EDA has the technology which ensures highest safety and security of the device by reducing the Test Application Time (thereby making its usable for tighter Diagnostic Time Interval). It provides the infrastructure for system software-based access to any test and diagnosis capabilities integrated within the system.

Remember the adage, a chain is only as strong as its weakest link, Siemens EDA’s technology offerings - Tessent MissionMode, LBIST/MBIST are all about ensuring that the ICs in your system won’t be that weak link. All of this coupled with highly automated process, customers can turn around the time to develop DFT architecture from months to days.

We welcome you to this session on DFT for Mission Critical ICs and provide you the latest knowhow on building safety critical ICs.

Key takeaways for you from this session

• How can you ensure safety of your device from random aging related defects?
• How can you effectively monitor your device health and ensure a swift response in case of failure?
• How not to degrade system performance while testing in-system?

Who can benefit from the webinar

• Design For Test engineers, Managers and Directors
• IC design engineers/managers
• CAD engineers
• Product & operations teams