DFT pattern simulation is a challenging and time-consuming task. Most of the time TB for scan inserted netlist generated from Tessent FS and TK are like an isolated island. DFT simulation setup has no connection with complex TB used for RTL or gate level verification. DFT pattern simulation can be effectively used with state of art Visualizer debugging platform and powerful Questa Sim simulator. Visualizer is a common debug platform for Tessent (DFT) – Questa Sim (Simulation) – Veloce (Emulation) which makes debugging easy.
DFT and pattern simulation tools are tightly integrated and that’s why it is important to have single-stop solutions for the flow. Siemens provides a comprehensive single-stop solution for DFT and Pattern simulation. Long-running zero delay patterns on emulation platform are very fast sometimes even grater then 100x w.r.t. simulation. Once the DFT simulation setup is ready on Questa Sim, it can be migrated to the Emulation platform easily. If you are already using Siemens Tessent tools for DFT the webinar will highlight various aspects/flows of Questa Sim simulations and visualizer debug flows to achieve higher productivity and performance for pattern simulations.
webinar will highlight the importance of a comprehensive single-stop solution for DFT and pattern simulation tools that are tightly integrated.
What will you learn
If you are already using Siemens Tessent tools for DFT the webinar will highlight various aspects/flows of Questa Sim simulations and visualizer debug flows to achieve higher productivity and performance for pattern simulations.
Who should attend
Field Application Engineering Manager - FV
Sachin has 19+ years of experience in the domain of IC design and verification.
Working with Siemens for the last 13+ years in solving customer verification problems.
Masters in Electronics and Telecommunication. Currently responsible for engaging with the design houses for Systematic Verification, Functional Safety (FuSa), Formal Verification, and DFT lead Simulations.