Early Design Verification

The event focuses on Productivity enhancement flows during the early phase of the design. When a design is incomplete or in very early stages, the goal does not have to be 100% sign-off clean but to find gross design flaws, which often lead to thousands or even millions of violations. Recon technologies focus on intelligent execution of DRC/LVS/ERC checks to minimize runtime with lesser hardware and lower memory footprint. RealTime technologies reduces the overall turn around time to identify and fix the DRC errors and get a better layout in less time.