Demystifying HLS for the RTL Design Team
Designing in SystemC or C++, applying High-Level Synthesis (HLS), and achieving quality of results (QoR) comparable to handwritten RTL is often met with much skepticism by design engineers and project management, even with countless success stories of HLS in multiple application domains.
In this webinar, we will present the workflow of Catapult® HLS, with the focus on step-by-step generation of optimized RTL from C. We’ll highlight the impact of users’ C-based modeling, how the basic HLS transformations work, and how the advanced analysis capabilities within the Catapult® HLS platform can be used to give the design engineer full control of the HLS process to achieve both productivity and QoR.
What you will learn:
- Step-by-step generation of optimized RTL from C
- Basic HLS transformations work
- Workflow of Catapult® HLS
- How the advanced analysis capabilities within the Catapult® HLS
platform can be used to give the design engineer full control of the
HLS process to achieve both productivity and QoR
Who should attend:
- RTL designers
- Hardware architects
- Managers
- Project Managers
Meet the speaker
Stuart Clubb
Technical Product Management Director
Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.