Converging High Performance Designs With Ease

Overview

There are specific challenges that must be considered in order to meet High Performance Computing (HPC) targets. Every step of the physical implementation flow needs to address PPA metrics and avoid pessimism because the margins for achieving design closure on HPC designs at signoff are very small.

Aprisa's innovative detail-route-centric architecture and patented technologies help designers reach their intended HPC targets, while reducing pessimism during P&R. Aprisa’s near signoff timing engine ensures excellent correlation with STA and DRC signoff tools, greatly reducing the number of ECO iterations, and avoiding overdesigning early in the flow and over-fixing late in the flow.

What you will learn

• Datapath skewing from place_opt to route_opt, to meet their challenging frequency targets.
  • We will cover how Aprisa’s detail-route-centric architecture makes it possible to derive the push and pull offsets during place_opt and effectively realize them in route_opt.

• Close correlation with Timing Signoff
• We will also cover how the patented technologies that make Aprisa correlate closely with STA and DRC Signoff tools, allow designers to adopt the flow very quickly for their advanced node designs.

• Single Flow for multiple blocks
• Designers can get started by simply entering the type of design and process in Aprisa’s Flow Generator, and Aprisa helps them achieve fast design closure and meet their PPA targets.

• Good riddance from manual and iterative tweaks
• This is done out-of-the-box, without the need to set placement guides, to set dozens of NDR rules, or even pre-generate via pillars.

You will learn about a case study for an HPC implemented through Aprisa at an advanced process node, and how the above technologies help achieve desired frequency target.