on-demand webinar

Cisco: RTL Power Optimization in a Tight Schedule: PowerPro Automatic RTL Write Capabilities in Vector-Less Mode

Estimated Watching Time: 18 minutes


Cisco: RTL Power Optimization - PowerPro in Vector-Less Mode

The cooling problem was a high priority issue in our Product. One way to address it was by reducing consumed power starting from the RTL phase. Our challenge was that RTL design was done and we had limited time for the power optimization. This is where PowerPro’s unique ability to automatically write power optimized RTL came in. Despite the absence of switching activity, PowerPro enabled us to target RTL power optimization where ordinarily we would have been limited back-end power optimization only. Given that back-end power optimization is known to be less effective than at RTL level, this was a big benefit to us. We used clock gating (CG) efficiency gains to measure PowerPro’s effectiveness. On several power hungry blocks, we achieved a CG efficiency gain of 10-20%. 

Meet the speaker


Udupi Harisharan

Sr. Tech Lead

Udupi Harisharan has worked on Networking Asics for the past 20 years taping out more than 15  Asics and Leads a team Focused on design and implementation including Asic Design methodologies involving Soc integration, Power optimization, Power Analysis and Emulation of the  Data center Asics at Cisco.

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