on-demand webinar

Alibaba: Innovating Agile Hardware Development with Catapult HLS

Estimated Watching Time: 32 minutes


At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.

The high cost and lengthy development cycle of chip design have significantly impeded innovation in the industry. Recent advancements in hardware description languages, domain-specific hardware accelerators, and AI-assisted EDA tools are propelling the chip design methodology towards a new era. This talk will showcase Alibaba's efforts to revolutionize agile chip development technologies on the IP and SoC levels using Catapult HLS.  

At the IP level, we adopted a software-hardware co-design approach to develop an image signal processor (ISP) with the help of Catapult HLS. While the tool provided significant benefits, the designer's experience and knowledge of the target architecture still played a significant role in selecting derivates. To address this challenge, we introduced an AI-assisted design space exploration (DSE) tool that automatically generates optimal solutions or trade-offs among different objectives under specific constraints. By leveraging Catapult HLS and our DSE tool, we successfully developed an efficient ISP with desired engineering quality within a year, a task that would have been impossible using traditional methods. Moving forward, we plan to open-source this HLS-based IP to foster extensive industry-academia collaboration and contribute to the community.  

On the SoC level, we developed an HLS-based AXI performance monitor that simplifies large-scale SoC performance test. Due to the limitations of RTL simulation (not scalable for complex SoC simulation) and TLM (not synthesizable if written in SystemVerilog), we deployed Catapult HLS and designed a synthesizable performance monitor in SystemC to capture AXI data transactions on a large-scale emulation platform. Under the hood, this module provides two modes: the first mode recording transaction details, and second mode outputs performance statistics. In summary, our HLS-based AXI performance monitor enables high-productivity full system hardware emulation, validation, and profiling, what is drastically helpful on SoC performance evaluation. 

Meet the speaker


Sicheng Li

Research Scientist

Sicheng Li is currently a Research Scientist in Computing Technology Lab at Alibaba DAMO Academy, Sunnyvale, CA, USA. He received his M.S. from New York University and Ph.D. from University of Pittsburgh. Before joining Alibaba, he also worked with HP Labs, Micron and an AI accelerator startup DEEPHi. His current research interests include electronic design automation, machine learning, domain-specific hardware architectures and FPGA. He has published 20+ technical papers in DAC, ICCAD, FCCM, NeurIPS, AAAI, Nature communications, etc.

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