on-demand webinar

AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS

Estimated Watching Time: 320 minutes


Seminar studies an AI/ML accelerator design in AMBA AXI-based subsystem, covering all steps from algorithm through C-based design & system-level performance validation, HW/SW integration, and verification via RTL coverage closure.

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. It is being used to create production-quality HW Accelerators for multiple applications such as 5G and Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent power, performance and area. Many new to HLS, however, have questions about how to take advantage of the productivity benefits of moving up in abstraction and still have the verification closure and confidence that they have with their current methodology.

This technical seminar is a case study of an AI/ML accelerator design in an AMBA AXI-based subsystem. It goes step-by-step from an algorithm through C-based design and system-level performance validation, HW/SW integration, and then comprehensive verification through RTL coverage closure showing both tools and methodology.

Seminar Introduction and Customer Case Studies  

This session will give an overview of the seminar and what you will learn. It will also present a high level introduction of the status of Catapult HLS capabilities today, high-level vision and roadmap and several customer case-studies from companies like NVIDIA, Google, Facebook, Microsoft, Horizon Robotics and more.
Speaker: Ellie Burns

High-Level Synthesis Design Intro and Benefits  

HLS enables designers to rapidly go from a high-level description in C++/SystemC to optimized RTL. This introduction session will show the basics around how high-level synthesis and Catapult HLS can be used to synthesize to optimal RTL for a production design flow.
Speaker: Michael Fingeroff

Intro to Modeling Performance and Verification with Synthesizable MatchLib 

MatchLib is a new open-source library written in SystemC and C++, originally created by NVIDIA, that enables much faster design and verification of SOCs using HLS. One of the primary objectives of MatchLib is easier performance accurate modeling of SOCs which enables designers to find system-level performance bottlenecks far sooner in their design cycle. This session will introduce MatchLib, and show how it enables designers to identify and resolve issues such as bus and memory contention, arbitration strategies, and optimal interconnect structure at a much higher level of abstraction than RTL.
Speaker: Stuart Swan

Early Performance Analysis and Architectural Optimization of a Machine Learning Accelerator Using MatchLib 

This session focuses on the design and optimization of a machine learning HW accelerator using MatchLib. The accelerator is designed to be part of a larger system, including a CPU, and uses MatchLib AXI4 master and slave interfaces to connect to the system bus. MatchLib and SystemC simulation is used to demonstrate how modelling performance early lets designers easily, and accurately, optimize and refine their hardware architecture prior to running synthesis.
Speaker: Michael Fingeroff

Automating High-Level Design Creation 

In this session you will learn how to create a MatchLib-based submodule using the COSIDE module editor and integrate it into a larger processor/memory subsystem. It will demonstrate how modules can be composed using the schematic editor and how a template for a testbench and stimuli can be generated. This session will also show how the design, including the MatchLib-based accelerator, can be simulated, analyzed, and debugged at an abstract level.
Speaker: Thomas Arndt, COSEDA

Quick Recap and High-Level Verification Introduction  

This session will give a brief summary of what we learned on Day 1. It will then introduce some of the verification benefits, concepts, choices and methodologies that can be used when your design is described in synthesizable HLS code written in C++/SystemC along with an introduction of the methodology and sessions for Day2.
Speaker: Ellie Burns

System Integration and Programming 

This session will show the final AI/ML accelerator being integrated into an ARM processor based platform using COSEDA Technology’s COSIDE development environment. It will include programming the accelerator from an application running on the ARM core, and measuring end-to-end inference performance as well as the co-simulation of abstract TLM based models with the RTL models of the HLS synthesized modules. Coseda’s COSIDE permits a fast and easy setup and simulation of complex virtual platforms as well as a gradual refinement towards implementation.
Speaker: Karsten Einwich, COSEDA

Intro to Questa Verification Management 

This session will introduce the concepts needed to manage today's verification process from build and regression management through coverage and results analysis and tracing and tracking against specification and a plan. It will highlight the Questa Verification Management suite of tools, methodology and Unified Coverage Database technology and roadmap that can deliver comprehensive solutions from C to RTL and desktop to cloud.
Speaker: Darron May

High-Level Verification Benefits, Tools and Methodology 

In conjunction with HLS, High-Level Verification (HLV) allows verification teams to verify designs sooner, at a higher level of abstraction, and in a more efficient manner than traditional RTL flows. Yet HLV is accomplished using known and trusted RTL verification techniques. This session will show the benefits of using high-level verification and introduce a family of Catapult HLV tools to verify HLS designs at the C-level.
Speaker: David Aerne

Achieving Verification Signoff within an HLS Flow 

Even with HLS, verification signoff still occurs at the RTL level. This session will demonstrate efficient re-use of the HLV flow highlighted in the previous session. This flow, when used along with a few additional approaches, will be used to quickly and deterministically achieve verification signoff requirements, including code and functional coverage closure, on the post-HLS RTL.
Speakers: Michael Fingeroff and David Aerne

Leveraging Formal Techniques to Help Verify HLS Models 

Formal techniques can be used in new and innovative ways to help speed verification of HLS models. This session will describe some new approaches to use formal techniques to help automate verification closure for HLS models.
Speaker: Stuart Swan

Meet the speakers

Siemens EDA

Ellie Burns

Former Director of Marketing

Ms. Burns has over 30 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She was formerly the Director of Marketing for the Calypto Systems' Division at Siemens EDA responsible for low-power RTL solutions with PowerPro and HLS Solutions with Catapult. Prior to Siemens and Mentor, Ms. Burns held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.

Siemens EDA

Michael Fingeroff

HLS Technologist

Michael Fingeroff has worked as an HLS Technologist for the Catapult High-Level Synthesis Platform at Siemens Digital Industries Software since 2002. His areas of interest include Machine Learning, DSP, and high-performance video hardware. Prior to working for Siemens Digital Industries Software, he worked as a hardware design engineer developing real-time broadband video systems. Mike Fingeroff received both his bachelor's and master's degrees in electrical engineering from Temple University in 1990 and 1995 respectively.

Siemens EDA

Stuart Swan

HLS Technologist

Stuart Swan is an HLS Technologist in the Catapult team, focusing on SoC modeling for High-Level Synthesis. Prior to Siemens EDA, Stuart worked for Qualcomm and Cadence. Stuart is co-author of the first book on SystemC, "System Design with SystemC," and was the IEEE technical chairman of the 2005 SystemC LRM. He received his BSEE from Stanford University.


Thomas Arnt

Application Engineering Manager

Thomas Arndt is an Application Manager at COSEDA Technologies, focusing on system level design and simulation solutions. He has over 20 years of experience in the chip design and the EDA industry. His particular areas of expertise are in the field of digital as well as analog system design, simulation and High-Level Synthesis. Prior to joining COSEDA, he was working at the Fraunhofer Institute for Integrated Circuits, one of the largest research institutions in the field of design automation in Europe. He received his diploma in electrical engineering from the Technical University of Dresden.

COSEDA Technologies

Karsten Einwich


Karsten Einwich is CEO of COSEDA Technologies, a company based in Germany that provides software solutions in the field of system level design for complex electronic hard- & software products. Karsten Einwich has more than 25 years of experience in the field of modelling, simulation and verification of complex heterogeneous systems. Prior to COSEDA, Karsten Einwich managed a research group at the Fraunhofer Institute for Integrated Circuits which developed methods and tools for the design of electronic hard- & software components in the context of the whole system. He was deeply involved in the development and standardization process (IEEE & Accellera) of the SystemC AMS modelling and simulation technology. His activities in various national and international industrial projects over the past 25 years have made him a highly recognized expert in in the field of how to make latest system modeling, simulation, design and verification methodologies efficient, practical and usable. He received his diploma in electrical engineering from the Technical University of Dresden.

Siemens EDA

Darron May

Product Marketing Manager

Darron May has over 30 years of experience in the electronics industry including board, FPGA, and chip design & verification, pre and post sales support, applications, consulting and technical marketing. As a Product Marketing Manager in the Design Verification Technology Division of Siemens EDA, Mr. May has most recently been focused on architecting Verification Management solutions based on customer requirements and driving the deployment of the tools worldwide. Prior to Siemens EDA, Mr. May has held positions in the engineering and applications management in the Datacoms and EDA industries, for Racal Datacom, Racal Research, Model Technology Inc., and through distribution including Synplicity, Summit Design, TSSI, InterHDL, and Simucad. Mr. May holds an HND in Electronic Engineering from Basingstoke college of technology.

Siemens EDA

David Aerne

Verification Technologist

Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.

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