AI/ML Accelerator Tutorial: C-level Design & Verification Using HLS

Catapult HLS (High-Level Synthesis) and C-level design and verification are reducing entire project development times by half or more in today’s ASIC and FPGA designs. It is being used to create production-quality HW Accelerators for multiple applications such as 5G and Communication, Image and Video Processing, Automotive, and AI/ML much faster than hand-coded RTL with equivalent power, performance and area. Many new to HLS, however, have questions about how to take advantage of the productivity benefits of moving up in abstraction and still have the verification closure and confidence that they have with their current methodology.

This technical seminar is a case study of an AI/ML accelerator design in an AMBA AXI-based subsystem. It goes step-by-step from an algorithm through C-based design and system-level performance validation, HW/SW integration, and then comprehensive verification through RTL coverage closure showing both tools and methodology.

Seminar Introduction and Customer Case Studies  

This session will give an overview of the seminar and what you will learn. It will also present a high level introduction of the status of Catapult HLS capabilities today, high-level vision and roadmap and several customer case-studies from companies like NVIDIA, Google, Facebook, Microsoft, Horizon Robotics and more.
Speaker: Ellie Burns

High-Level Synthesis Design Intro and Benefits  

HLS enables designers to rapidly go from a high-level description in C++/SystemC to optimized RTL. This introduction session will show the basics around how high-level synthesis and Catapult HLS can be used to synthesize to optimal RTL for a production design flow.
Speaker: Michael Fingeroff

Intro to Modeling Performance and Verification with Synthesizable MatchLib 

MatchLib is a new open-source library written in SystemC and C++, originally created by NVIDIA, that enables much faster design and verification of SOCs using HLS. One of the primary objectives of MatchLib is easier performance accurate modeling of SOCs which enables designers to find system-level performance bottlenecks far sooner in their design cycle. This session will introduce MatchLib, and show how it enables designers to identify and resolve issues such as bus and memory contention, arbitration strategies, and optimal interconnect structure at a much higher level of abstraction than RTL.
Speaker: Stuart Swan

Early Performance Analysis and Architectural Optimization of a Machine Learning Accelerator Using MatchLib 

This session focuses on the design and optimization of a machine learning HW accelerator using MatchLib. The accelerator is designed to be part of a larger system, including a CPU, and uses MatchLib AXI4 master and slave interfaces to connect to the system bus. MatchLib and SystemC simulation is used to demonstrate how modelling performance early lets designers easily, and accurately, optimize and refine their hardware architecture prior to running synthesis.
Speaker: Michael Fingeroff

Automating High-Level Design Creation 

In this session you will learn how to create a MatchLib-based submodule using the COSIDE module editor and integrate it into a larger processor/memory subsystem. It will demonstrate how modules can be composed using the schematic editor and how a template for a testbench and stimuli can be generated. This session will also show how the design, including the MatchLib-based accelerator, can be simulated, analyzed, and debugged at an abstract level.
Speaker: Thomas Arndt, COSEDA

Quick Recap and High-Level Verification Introduction  

This session will give a brief summary of what we learned on Day 1. It will then introduce some of the verification benefits, concepts, choices and methodologies that can be used when your design is described in synthesizable HLS code written in C++/SystemC along with an introduction of the methodology and sessions for Day2.
Speaker: Ellie Burns

System Integration and Programming 

This session will show the final AI/ML accelerator being integrated into an ARM processor based platform using COSEDA Technology’s COSIDE development environment. It will include programming the accelerator from an application running on the ARM core, and measuring end-to-end inference performance as well as the co-simulation of abstract TLM based models with the RTL models of the HLS synthesized modules. Coseda’s COSIDE permits a fast and easy setup and simulation of complex virtual platforms as well as a gradual refinement towards implementation.
Speaker: Karsten Einwich, COSEDA

Intro to Questa Verification Management 

This session will introduce the concepts needed to manage today's verification process from build and regression management through coverage and results analysis and tracing and tracking against specification and a plan. It will highlight the Questa Verification Management suite of tools, methodology and Unified Coverage Database technology and roadmap that can deliver comprehensive solutions from C to RTL and desktop to cloud.
Speaker: Darron May

High-Level Verification Benefits, Tools and Methodology 

In conjunction with HLS, High-Level Verification (HLV) allows verification teams to verify designs sooner, at a higher level of abstraction, and in a more efficient manner than traditional RTL flows. Yet HLV is accomplished using known and trusted RTL verification techniques. This session will show the benefits of using high-level verification and introduce a family of Catapult HLV tools to verify HLS designs at the C-level.
Speaker: David Aerne

Achieving Verification Signoff within an HLS Flow 

Even with HLS, verification signoff still occurs at the RTL level. This session will demonstrate efficient re-use of the HLV flow highlighted in the previous session. This flow, when used along with a few additional approaches, will be used to quickly and deterministically achieve verification signoff requirements, including code and functional coverage closure, on the post-HLS RTL.
Speakers: Michael Fingeroff and David Aerne

Leveraging Formal Techniques to Help Verify HLS Models 

Formal techniques can be used in new and innovative ways to help speed verification of HLS models. This session will describe some new approaches to use formal techniques to help automate verification closure for HLS models.
Speaker: Stuart Swan