A Predictable and Automated Path to Low-Power RTL
RTL power optimization efforts are too often traded to meet project deadlines. Manually combing through thousands of lines of code to find power saving opportunities is a hard and time consuming process. PowerPro eliminates all of that tedious work by automatically optimizing your RTL design to save up to 30% with no impact to timing or area. In this webinar, we will explain how PowerPro consistently produces better results than manual efforts and in significantly less time. You will also learn how PowerPro complies with stringent ASIC flow requirements with its built-in formal verification and ECO support. Used by leading semiconductor and fabless companies around the world, PowerPro is the ideal solution to effortlessly meet power goals on your next SoC project without sacrificing your schedule.
Who Should View
- RTL designers
- Power architects
- Project managers
- Engineers needing to reduce dynamic power but with little time or resources to do so
What You Will Learn
- Why power estimation is necessary but not sufficient
- Challenges with RTL power optimization
- Overview of the PowerPro platform
- Requirements of an automatic power optimization flow
- Maximizing power savings without impacting timing or area
- Verifying power optimized RTL
- ECO's on automatically optimized RTL
- Examples and customer results
Meet the speaker
Ellie Burns
Former Director of Marketing
Ms. Burns has over 30 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She was formerly the Director of Marketing for the Calypto Systems' Division at Siemens EDA responsible for low-power RTL solutions with PowerPro and HLS Solutions with Catapult. Prior to Siemens and Mentor, Ms. Burns held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.