Heterogeneous Design Methods for 3D IC

Deciding to use chiplets and heterogeneous integration to form a System-in-Package (SiP) that can outperform a monolithic approach requires a significantly different approach from micro-architecture partitioning through prototyping/planning an optimum scenario down to detailed integration and implementation, verification, and signoff. 

Tony Mastroianni, Advanced Packaging Solutions Director at Siemens DISW, discusses the tremendous benefits of heterogeneous integration that enables greater system integration and improves power performance area (PPA) and form factors. He also discusses the importance or addressing optimal system level decomposition, power delivery network (PDN) design, power integrity (PI) analysis as well as the challenges associated with multi-die timing, signal integrity analysis and ATE testing.

This session will outline 5 key workflows that enable new or seasoned semiconductor design team to get their chiplet-based designs to meet their product and business goals in a timely and efficient manner.

• Architectural planning and analysis
• Physical design planning and analysis
• Design analysis
• Reliability analysis
• Test planning and validation