On-Demand Webinar

Designing SerDes channels for protocol compliance

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Multi-gigabit serial channels present some of the most stringent signal integrity challenges facing designers today. With high-speed links, small details are critical – device pinout, breakout routing, signal routing layers, return paths, and parasitics associated with blocking capacitors all have a significant impact on channel margin that requires careful design analysis and optimization. Equally important is avoiding analytical overkill – spending too much time optimizing a single structure without considering its impact on total channel margin – because over-optimization wastes time and money.

This webinar explores the different aspects of serial channel design planning and analysis from the pre-layout standpoint, using simulation to develop a detailed set of layout rules. Design of detailed geometries requiring 3D EM simulation is explored, showing how to assess design alternatives and maximize overall channel margin.

What you will learn:

  • SerDes channel concepts & terminology

  • Different types of SerDes channel compliance analysis

  • Compliance analysis using Channel Operating Margin (COM)

  • Evaluating SerDes channels for protocol compliance

  • How progressive analysis helps speed the design process

  • Creating, parameterizing, and analyzing 3D areas

  • Optimizing via designs, blocking capacitor, and BGA breakouts

  • Avoiding analytical overkill by focusing on overall channel margin

Who should attend:

  • PCB/System Designers

  • Engineering Managers

  • Signal Integrity Specialists

  • PCB Layout Designers

Products covered:

  • HyperLynx Signal Integrity