Ensuring DDR4 Electrical Performance at Intended Data-rate

This webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.

Overview

DDR interfaces have many signal integrity and timing requirements that
need to be guaranteed between multiple signal groups. Conformance to
the requirements should be verified before a board is fabricated to
reduce the chance of prototype spins. Traditionally, designers have
relied on dedicated SI experts to perform this task, or laid out
boards based on manufacturer’s guidelines and skipped post-route
verification entirely, hoping to avoid problems in the lab. Increasing
data rates have pushed DDR operating margins to the point where simply
following physical design rules is no longer enough to ensure that a
design will work as intended.

This webinar will discuss the different electrical requirements
associated with DDR designs and show how board and system designers
can use HyperLynx to perform post-route verification themselves,
helping free up scarce SI experts to focus on their company’s most
challenging analysis problems.

What will you learn:

• DDR electrical requirements for signal integrity and timing
• Why “routing by the rules” isn’t enough anymore
• Why JEDEC specifications only give you half of the information you
  need
• How Controller/DRAM configuration affects routing requirements
• How to use HyperLynx post-route verification to optimize margins for
  designs as-routed

Who should view:

• PCB/System Designers
• Engineering Managers
• Signal Integrity Specialists
• PCB Layout Designers