From Python to High-Performance AI Accelerators
Designing AI inference hardware for edge applications often requires building custom hardware accelerated solutions to meet the demands for ultra-low power consumption and strict real-time response requirements. This webinar introduces Catapult AI NN, which provides an automated flow that starts with a Python neural network model and generates an RTL hardware accelerator. The flow enables rapid exploration of design alternatives, helping teams identify the right implementation that best meets their Power, Performance, and Area goals.
What you will learn:
- How to create an RTL hardware accelerator from a Python/Keras neural network model using Catapult AI/NN.
- How to optimize the accelerator implementation through parallelization, pipelining, and resource sharing.
- How to explore architectural alternatives to achieve your PPA goals.
- How to target your design to either FPGA or ASIC.
- How to integrate your hardware accelerator into a RISC-V processing sub-system.
Who should view:
- Hardware designers developing inferencing systems for edge or ultra low-power solutions.
- System architects exploring trade-offs between hardware performance, power, area, and cost.
- Project owners looking to accelerate their hardware design process.
Lernen Sie die Referierenden kennen
Russell Klein
HLS Program Director
Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor.
Matthew Bone
High-Level Synthesis Technologist
Matthew Bone is a High-Level Synthesis Technologist at Siemens EDA, with focus on the Catapult HLS design platform. His areas of expertise include hardware accelerator development, HW/SW co-design, and design-space exploration to find best architecture and PPA solutions. Matt has 25+ years experience in digital design and verification, with developed products including CPUs, high-speed interfaces, wireless communication devices, and DSP/ML accelerators. Prior to joining Siemens EDA in 2024, Matt held roles at silicon design companies including Intel, Micron, and Texas Instruments.